Digital Design With an Introduction to the Verilog HDL FIFTH EDITION M. Morris Mano Emeritus Professor of Computer Engineering California State University, Los Angeles Michael D. Ciletti Emeritus Professor of Electrical and Computer Engineering University of Colorado at Colorado Springs Upper Saddle River Boston Columbus San Franciso New York Indianapolis London Toronto Sydney Singapore Tokyo Montreal Dubai Madrid Hong Kong Mexico City Munich Paris Amsterdam Cape Town.Contents vii 7 Memor y and Programmable Logic 299 7.1 Introduction 299 7.2 Random‐Access Memory 300 7.3 Memory Decoding 307 7.4 Error Detection and Correction 312 7.5 Read‐Only Memory 315 7.6 Programmable Logic Array 321 7.7 Programmable Array Logic 325 7.8 Sequential Programmable Devices 329 8 De s i gn at the Register Transfer Level 351 8.1 Introduction 351 8.2 Register Transfer Level Notation 351 8.3 Register Transfer Level in HDL 354 8.4 Algorithmic State Machines (ASMs) 363 8.5 Design Example (ASMD Chart) 371 8.6 HDL Description of Design Example 381 8.7 Sequential Binary Multiplier 391 8.8 Control Logic 396 8.9 HDL Description of Binary Multiplier 402 8.10 Design with Multiplexers 411 8.11 Race‐Free Design (Software Race Conditions) 422 8.12 Latch‐Free Design (Why Waste Silicon?) 425 8.13 Other Language Features 426 9 L aborator y Experiments wi t h Standard ICs and FPGAs 438 9.1 Introduction to Experiments 438 9.2 Experiment 1: Binary and Decimal Numbers 443 9.3 Experiment 2: Digital Logic Gates 446 9.4 Experiment 3: Simplification of Boolean Functions 448 9.5 Experiment 4: Combinational Circuits 450 9.6 Experiment 5: Code Converters 452 9.7 Experiment 6: Design with Multiplexers 453 9.8 Experiment 7: Adders and Subtractors 455 9.9 Experiment 8: Flip‐Flops 457 9.10 Experiment 9: Sequential Circuits 460 9.11 Experiment 10: Counters 461 9.12 Experiment 11: Shift Registers 463 9.13 Experiment 12: Serial Addition 466 9.14 Experiment 13: Memory Unit 467 9.15 Experiment 14: Lamp Handball 469
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